The present invention relates generally to decoders and more specifically to an improved word line driver and latch for a decoder.
A word line decoder, as illustrated in FIG. 1 generally includes a decoding section 12, a line driver section 14 and a latch 16.
The decoder portion 12 includes a plurality of decoder transistors P1 through P7 having their source and drain paths connected in parallel and each one uniquely receiving word address AW on their gates. The sources of the decoder devices P1 through P7 are connected to a voltage supply VCC by a transistor P8 whose gate is controlled by a decoder enable signal DE. The drains of the address decoders P1 through P7 are connected to the drain of precharge transistor N1 whose source is ground and whose gate is controlled by the decoder enable signal DE. The line driver 14 is a CMOS inverter including P9 and N2 wherein the source of P9 is connected to the word signal WDS. A precharge transistor N3, whose source is grounded and whose gate receives the decoder enable signal DE, precharges the word line WL low. The latch 16 includes transistor N4 having its drain connected to the input of the inverter P9-N2, its source connected to ground and its gate connected to the word line WL.
In a normal operation cycle of the decoder of FIG. 1, the decoder enable signal DE is high turning off P8 and turning on N1 and N3. This disconnects the supply voltage VCC from the decoder portion 12, removes any charge or current on the drains of the decoder transistors P1-P7, and precharges the word line WL low, respectively. This generally occurs from T0 through T25. Also during this first period, the addresses lines AW applied to the gates of P1 through P7 can be changed as illustrated by the transition in FIG. 2. The next portion of this cycle is when the decoder enable signal DE goes low turning on P8 and turning off N1 and N3. This enables the decoder section 12. The decoder enable DE stays low for the remainder of the cycle from T25 to T200. If the unique address of the decoder section 12 is received, the word line driver 14 provides the word signal WDS as a word line signal along word line WL. The word signal WDS is delayed from T25 to T75 to allow sufficient time for the address decoder transistors P1 through P7 to pull the gate of the word line drive P9 high which disables all non decoded word line drivers. The latch 16 operates in response to a word line high signal to latch the input of the word line driver 14. The timing graphs are illustrated in FIG. 2.
It can be seen that the cycle generally includes a precharge or deaccess cycle during which the address is changed followed by an access or enable or line drive cycle. The precharge and address change cycles are inter-related and cannot be performed independently, since the word line drive is an integral part of the latch. Thus, the period needed to perform the cycles is longer than desired. Thus, there exists the need for a new address decoder architecture which will allow for a decrease in the total cycle of the address decoder.